User profiles for Chung-Chuan Lo
Chung-Chuan LoNational Tsing Hua University Verified email at mx.nthu.edu.tw Cited by 3278 |
Cortico–basal ganglia circuit mechanism for a decision threshold in reaction time tasks
Growing evidence from primate neurophysiology and modeling indicates that in reaction
time tasks, a perceptual choice is made when the firing rate of a selective cortical neural …
time tasks, a perceptual choice is made when the firing rate of a selective cortical neural …
16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices
…, CJ Jhang, CI Su, WS Khwa, CC Lo… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
Battery-powered tiny-AI edge devices require large-capacity nonvolatile compute-in-memory
(nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex …
(nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex …
Common scale-invariant patterns of sleep–wake transitions across mammalian species
Although mammals of different species have different sleep patterns, brief sleep–wake
transitions commonly are observed across species and appear to occur randomly throughout the …
transitions commonly are observed across species and appear to occur randomly throughout the …
24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors
…, SY Wei, YC Chiu, CY Lee, CC Lo… - … Solid-State Circuits …, 2019 - ieeexplore.ieee.org
Embedded nonvolatile memory (NVM) and computing-in-memory (CIM) are significantly
reducing the latency (t MAC ) and energy consumption (E MAC ) of multiply- and-accumulate (…
reducing the latency (t MAC ) and energy consumption (E MAC ) of multiply- and-accumulate (…
16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips
Recent SRAM-based computation-in-memory (CIM) macros enable mid-to-high precision
multiply-and-accumulate (MAC) operations with improved energy efficiency using ultra-small/…
multiply-and-accumulate (MAC) operations with improved energy efficiency using ultra-small/…
A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices
Non-volatile computing-in-memory (nvCIM) architecture can reduce the latency and energy
consumption of artificial intelligence computation by minimizing the movement of data …
consumption of artificial intelligence computation by minimizing the movement of data …
[HTML][HTML] SYNAPSE: An international roadmap to large brain imaging
Since 2020, synchrotron radiation facilities in several Asia-Pacific countries have been
collaborating in a major project called “SYNAPSE” (Synchrotrons for Neuroscience: an Asia-…
collaborating in a major project called “SYNAPSE” (Synchrotrons for Neuroscience: an Asia-…
15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices
…, YK Chen, YC Lo, TH Wen, CC Lo… - … Solid-State Circuits …, 2020 - ieeexplore.ieee.org
Nonvolatile computing-in-memory (nvCIM) can improve the latency (t AC ) and energy-efficiency
(EF MAC ) of tiny AI edge devices performing multiply-and-accumulate (MAC) …
(EF MAC ) of tiny AI edge devices performing multiply-and-accumulate (MAC) …
15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips
…, Z Zhang, SH Sie, WC Wei, YC Lo… - … solid-state circuits …, 2020 - ieeexplore.ieee.org
Advanced AI edge chips require multibit input (IN), weight (W), and output (OUT) for CNN
multiply-and-accumulate (MAC) operations to achieve an inference accuracy that is sufficient …
multiply-and-accumulate (MAC) operations to achieve an inference accuracy that is sufficient …
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
…, TH Hsu, YK Chen, YC Lo, TH Wen, CC Lo… - Nature …, 2021 - nature.com
The development of small, energy-efficient artificial intelligence edge devices is limited in
conventional computing architectures by the need to transfer data between the processor and …
conventional computing architectures by the need to transfer data between the processor and …