User profiles for David Blaauw

David Blaauw

Professor of Electrical Engineering and Computer Science, University of Michigan
Verified email at umich.edu
Cited by 44635

Statistical timing analysis for intra-die process variations with spatial correlations

A Agarwal, D Blaauw, V Zolotov - ICCAD-2003. International …, 2003 - ieeexplore.ieee.org
Process variations have become a critical issue in performance verification of high-performance
designs. We present a new, statistical timing analysis method that accounts for inter- …

Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits

RG Dreslinski, M Wieckowski, D Blaauw… - Proceedings of the …, 2010 - ieeexplore.ieee.org
Power has become the primary design constraint for chip designers today. While Moore's
law continues to provide additional transistors, power budgets have begun to prohibit those …

Hardware designs for security in ultra-low-power IoT systems: An overview and survey

K Yang, D Blaauw, D Sylvester - IEEE Micro, 2017 - ieeexplore.ieee.org
The development of ultra-low-power (ULP) electronic devices has opened up opportunities
for disruptive systems like the Internet of Things (IoT). The main concern is the security and …

Opportunities and challenges for better than worst-case design

T Austin, V Bertacco, D Blaauw, T Mudge - … of the 2005 Asia and South …, 2005 - dl.acm.org
The progressive trend of fabrication technologies towards the nanometer regime has created
a number of new physical design challenges for computer architects. Design complexity, …

Drowsy caches: simple techniques for reducing leakage power

K Flautner, NS Kim, S Martin, D Blaauw… - ACM SIGARCH …, 2002 - dl.acm.org
On-chip caches represent a sizable fraction of the total power consumption of microprocessors.
Although large caches can significantly improve performance, they have the potential to …

Razor: A low-power pipeline based on circuit-level timing speculation

…, R Rao, T Pham, C Ziesler, D Blaauw… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
With increasing clock frequencies and silicon integration, power aware computing has become
a critical concern in the design of embedded processors and systems-on-chip. One of the …

RazorII: In situ error detection and correction for PVT and SER tolerance

…, K Lai, DM Bull, DT Blaauw - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
Traditional adaptive methods that compensate for PVT variations need safety margins and
cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) …

A self-tuning DVS processor using delay-error detection and correction

…, D Roberts, S Lee, S Pant, D Blaauw… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which
incorporates an in situ error detection and correction mechanism to recover from timing errors. …

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

SM Martin, K Flautner, T Mudge, D Blaauw - Proceedings of the 2002 …, 2002 - dl.acm.org
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak
performance is unnecessary. However, the achievable power savings by DVS alone is …

A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V

M Seok, G Kim, D Blaauw… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
Sensing systems such as biomedical implants, infrastructure monitoring systems, and military
surveillance units are constrained to consume only picowatts to nanowatts in standby and …