User profiles for David Blaauw
David BlaauwProfessor of Electrical Engineering and Computer Science, University of Michigan Verified email at umich.edu Cited by 44635 |
Statistical timing analysis for intra-die process variations with spatial correlations
A Agarwal, D Blaauw, V Zolotov - ICCAD-2003. International …, 2003 - ieeexplore.ieee.org
Process variations have become a critical issue in performance verification of high-performance
designs. We present a new, statistical timing analysis method that accounts for inter- …
designs. We present a new, statistical timing analysis method that accounts for inter- …
Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
RG Dreslinski, M Wieckowski, D Blaauw… - Proceedings of the …, 2010 - ieeexplore.ieee.org
Power has become the primary design constraint for chip designers today. While Moore's
law continues to provide additional transistors, power budgets have begun to prohibit those …
law continues to provide additional transistors, power budgets have begun to prohibit those …
Hardware designs for security in ultra-low-power IoT systems: An overview and survey
The development of ultra-low-power (ULP) electronic devices has opened up opportunities
for disruptive systems like the Internet of Things (IoT). The main concern is the security and …
for disruptive systems like the Internet of Things (IoT). The main concern is the security and …
Opportunities and challenges for better than worst-case design
The progressive trend of fabrication technologies towards the nanometer regime has created
a number of new physical design challenges for computer architects. Design complexity, …
a number of new physical design challenges for computer architects. Design complexity, …
Drowsy caches: simple techniques for reducing leakage power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors.
Although large caches can significantly improve performance, they have the potential to …
Although large caches can significantly improve performance, they have the potential to …
Razor: A low-power pipeline based on circuit-level timing speculation
…, R Rao, T Pham, C Ziesler, D Blaauw… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
With increasing clock frequencies and silicon integration, power aware computing has become
a critical concern in the design of embedded processors and systems-on-chip. One of the …
a critical concern in the design of embedded processors and systems-on-chip. One of the …
RazorII: In situ error detection and correction for PVT and SER tolerance
Traditional adaptive methods that compensate for PVT variations need safety margins and
cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) …
cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) …
A self-tuning DVS processor using delay-error detection and correction
In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which
incorporates an in situ error detection and correction mechanism to recover from timing errors. …
incorporates an in situ error detection and correction mechanism to recover from timing errors. …
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak
performance is unnecessary. However, the achievable power savings by DVS alone is …
performance is unnecessary. However, the achievable power savings by DVS alone is …
A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V
Sensing systems such as biomedical implants, infrastructure monitoring systems, and military
surveillance units are constrained to consume only picowatts to nanowatts in standby and …
surveillance units are constrained to consume only picowatts to nanowatts in standby and …