The ratio of cpu speed to memory speed in current high-performance computers is growing
rapidly, with significant implications for the design and implementation of algorithms in …

We develop a generalizable AI-driven workflow that leverages heterogeneous HPC resources
to explore the time-dependent dynamics of molecular systems. We use this workflow to …

The HPC Challenge1 benchmark suite has been released by the DARPA HPCS program to
help define the performance boundaries of future Petascale computing systems. HPC …

We seek to completely revise current models of airborne transmission of respiratory viruses
by providing never-before-seen atomic-level views of the SARS-CoV-2 virus within a …

∎ Vector machines like the Cray X/MP, Cray Y/MP, Cray C90, CDC Cyber 205, ETA-10, and
various Japanese vector systems were built to this target of 12 Bytes/second of peak …

HPC systems are notorious for operating at a small fraction of their peak performance, and
the ongoing migration to multi-core and multi-socket compute nodes further complicates …

The HPCChallenge suite of benchmarks will examine the performance of HPC architectures
using kernels with memory access patterns more challenging than those of the High …

This paper studies microarchitectural side-channel attacks and mitigations on the on-chip
mesh interconnect used in modern, server-class Intel processors. We find that, though difficult …

In stratified three‐dimensional models the use of a boundary‐fitted vertical co‐ordinate is
known to produce errors in the horizontal pressure gradient calculation near steep topography. …

As the gap between proessor and main memory speed ontinues to grow, higher ahe hit
rates are required for eÆient proessor use. Re-ent work on ompile-time transformations to …