User profiles for L. Pipes

Lenore Pipes

Verified email at berkeley.edu
Cited by 767

A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging

…, C Parker, D Parsons, C Prasad, L Pipes… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate
transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-…

An operational analysis of traffic dynamics

LA Pipes - Journal of applied physics, 1953 - pubs.aip.org
… If the separation law of the California Vehicle Code is taken as an example, then the"
speedometer distance" TVk+l has the magnitude of 15 ft when the vehicle speed is ten miles per …

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

…, J Neirynck, C Parker, L Pipes… - 2012 symposium on …, 2012 - ieeexplore.ieee.org
A 22nm generation logic technology is described incorporating fully-depleted tri-gate
transistors for the first time. These transistors feature a 3 rd -generation high-k + metal-gate …

A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

…, P Patel, R Patel, C Pelto, L Pipes… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin
doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-…

[BOOK][B] Applied mathematics for engineers and physicists

LA Pipes, LR Harvill - 2014 - books.google.com
Pipes. It is one of three major texts for engineers and physicists with the other two being
Advanced … As seen in the example above, the contour c was deformed into the contour c l. …

A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and …

…, S Parthasarathy, C Pelto, L Pipes… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad
Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local …

High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

…, J Neirynck, S Pae, C Parker, L Pipes… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
A 32nm logic technology for high performance microprocessors is described. 2 nd generation
high-k + metal gate transistors provide record drive currents at the tightest gate pitch …

A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

…, S Pae, C Parker, C Pelto, L Pipes… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
A 32 nm generation logic technology is described incorporating 2 nd -generation high-k +
metal-gate technology, 193 nm immersion lithography for critical patterning layers, and …

Car following models and the fundamental diagram of road traffic

LA Pipes - Transportation Research/UK/, 1966 - trid.trb.org
THE DYNAMICS OF TRAFFIC FLOW WERE STUDIED TO DEVELOP A BETTER UNDERSTANDING
OF HOW TO COPE WITH THE TREMENDOUS VOLUME OF VEHICULAR TRAFFIC…

AutoDecon: a robust numerical method for the quantification of pulsatile events

ML Johnson, L Pipes, PP Veldhuis, LS Farhy… - Methods in …, 2009 - Elsevier
This work presents a new approach to the analysis of aperiodic pulsatile heteroscedastic
time-series data, specifically hormone pulsatility. We have utilized growth hormone (GH) …